Dataflow QNN inference accelerator examples on FPGAs
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Updated
Mar 10, 2026 - Python
Dataflow QNN inference accelerator examples on FPGAs
See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
Context on Git - High-density, token-optimized LLM context engine for hardware and software repositories
A Tool for Parallel Processing of ROS2 Hardware Acceleration on Zynq
Real-time bitstream malware detection using an ML model. Includes feature extraction, Trojan detection, family classification, and embedded inference on PYNQ-supported FPGA boards.
Scenario-adaptive video enhancement on PYNQ-Z2: OV5640 -> AXI4-Stream ISP -> VDMA -> HDMI with Q8.8 MLP and quadrant-based spatial decisions.
Deploying Deep Learning on FPGA: an assessment of ConvNets performance on Xilinx Zynq MPSoC using Vitis-AI development platform
This is a Smart_Lock Project using Ultra96_V2 and PYNQ.
Interactive real-time 1 MSPS Oscilloscope dashboard and Python package for PYNQ boards with Digilent AD3 wave generator integration.
See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.
跌倒识别与环境智控系统|AC880 / Zynq-7020|FPGA 创新设计竞赛自主选题初级组
Autonomous line-following robot on the Ultra96-V2 that recognizes traffic signs (GTSRB) in real time using a quantized neural network accelerated on the FPGA with FINN.
Real-time exercise detection system using a custom MLP on a Xilinx Zynq FPGA with MoveNet keypoint inference on the ARM processing system
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